The present invention relates generally to performing division and in particular, to a method and apparatus for performing division in hardware.
An operation which is often avoided in hardware implementations is the divide operation. This operation is most often avoided because of the processing time required to execute the operation. For example, prior art dividers perform long division via a xe2x80x9cconditional subtractxe2x80x9d algorithm, requiring at least 2N clocks, where N is the number of dividend bits. In order to solve this problem, prior art systems approximate a division using a multiplication algorithm. However, as system performance requirements increase, approximations of mathematical operations are becoming less tolerable. Therefore, a need exists for a method and apparatus for performing division in hardware that requires relatively little processing time, and yields a more accurate result than current approximation methods.